1. Field of the Invention
The present invention relates to a multiprocessor system having a shared memory and, more particularly, to a multiprocessor system, in which each processor element has a dedicated arbiter and a shared memory between itself and its upper processor element, and a method therefor.
2. Description of the Prior Art
In a prior art, the multiprocessor system having the shared memory is known as exemplified by "Nikkei Electronics, Vol. 407 (issued on Nov. 3, 1986)", pp. 119 to 129. FIG. 4 is a block diagram showing the schematic structure of the aforementioned system of the prior art.
In the microprocessor system having the shared memory according to the prior art, as shown in FIG. 4, one shared memory is connected with a common bus between two or more microprocessor units CPU 1, CPU 2, - - -, and so on, and a bus arbiter is also connected for arbitrating the conflict of the access to the shared memory.
In the above-specified conventional system, the capacity of the shared memory is limited to the address space (i.e., the address width capable of being expressed in the bit width of the shared bus) of the shared bus, thus raising a problem of shortage of its expandability. In order to expand and increase the size of the system thereby to improve the processing performance, more specifically, it is conceivable to expand and augment the memory capacity and to increase the number of the processor elements (i.e., the CPU 1, the CPU 2, - - -, and so on). In the system of the prior art, however, a shared memory in an external position is accessed from each processor element through the common arbiter and the common external bus so that any expanded system cannot be realized due to the bottleneck of the common bus even if the number of CPUs or the capacity of the memory is merely increased. In other words, the accesses of the individual CPUs conflict one another so that the processing performance (or throughput) matching the number of the CPUs cannot be attained even if only the number of the CPUs is increased while leaving the common bus as it is. It is also conceivable to reform the arbiter and the bus wiring together with the increases in the number of the CPUs and in the memory capacity so that the performance of the system in its entirety may be enhanced. However, this concept requires much labor and high cost, and it is uneconomical for preparing system for expansion in the future by disposing a bus having a wide address in advance.
Thus, in the existing multiprocessor system of the shared memory type, the maximum access space of the shared memory is equal to the address space of the common bus, which has its size limited thus making it difficult to subsequently increase the real memory capacity. In this system, moreover, one OS shared among a plurality of processors is arranged over the shared memory so as to centralize the management of the shared memory. As a result, the bus accessing frequency is increased to limit the number of processors to be added so as to eliminate the aforementioned bus bottleneck, thus limiting realization of a new function.
On the other hand, range of the data to be accessed by each processor is not efficient despite many parts proper to each processor, if the centralized shared memory is always used for such data. It is, therefore, desirable to distribute the functions of the individual processors to eliminate the centralization of the data while retaining the merits of the centralized system of the prior art.